This invention relates to a circuit with which a bus to be precharged inside a large scale integrated circuit can be divided and combined.
Large scale integrated circuits which are incorporated in microcomputers and the like are provided with buses for transferring data among their functional blocks such as the central processing unit, memory devices and I/O interface circuits. Such buses are frequently precharged to a high (H) level or a low (L) level. FIG. 3 shows an example of circuit for precharging a bus 1 to H level by a PMOS transistor 2 and FIG. 4 is a timing chart of the bus 1 of FIG. 3, showing that the bus 1 is charged to the H level in synchronism with clock signal .phi. applied to the gate of the PMOS transistor 2. After the bus 1 has been thus precharged to H level and when the bus driving signal BD applied to a bus driving circuit 3 is at H level, if a data signal D intended to be transmitted is at H level, the bus 1 remains in H level but if the data signal to be transmitted through the bus 1 is in L level, the bus driving circuit 3 operates to reduce the load capacitance of the bus 1. Speed of this operations depends on the driving power of this bus driving circuit 3.
If a bus is connected to many functional blocks of a large scale integrated circuit, for example, and is made very long, its load capacitance is also large. If its load capacitance becomes large and a more powerful bus driving circuit is required. Moreover, the driving force of the MOS transistor for precharging must also be increased in order to reduce the time for charging the bus to H level. In order to increase the driving power of the bus driving circuit or that of the MOS transistor for precharging, however, the bus driving circuit or the transistor must be made larger but it is not desirable from the point of view of large scale integration.
FIG. 5 shows another circuit structure characterized as having a resistive component 6 connected in series with a bus 5, bus driving circuit 7 and 8 to drive load capacitance 9 and another bus driving circuit 10 to drive load capacitance 11. In this case, the sum of the resistance of the bus driving circuits and that of the resistive component 6 controls the speed of the bus operation. Thus, for example, the resistance of the resistive component 6 cannot be compensated for by merely increasing the driving power as done in the case of FIG. 3. In other words, high-speed operation of the bus 5 is difficult to achieve.